The present invention relates to a semiconductor memory device having a capacitor, and a manufacturing method thereof, and more particularly, to a semiconductor memory device having a capacitor and manufacturing method thereof having a novel structure in which the surface area of a storage electrode of the capacitor is increased. The present invention is an improvement over the invention which is the subject matter of the applicant's pending U.S. patent application Ser. No. 07/937,749 filed on Sep. 1, 1992, the disclosure of which is hereby incorporated into this application by reference.
With the continuous development of fabrication technology for semiconductor devices and with the expansion of the applications for memory devices, the development of large-capacity memory devices is being carried out at a brisk pace. Particularly, a dynamic random access memory (DRAM) device, which consists of one memory cell and one capacitor and is thus well-suited to high integration, has been remarkably developed in terms of packing density.
The packing density of such a DRAM has been further integrated by a factor of four within a span of three years. At present, in the DRAM field, 4 Mb DRAMs are in mass production and 16 Mb DRAMs are soon to be produced in large quantities. Further, the 64 Mb DRAM and 256 Mb DRAM are being actively studied for mass production.
These semiconductor memory devices should have large capacitances for the reading out and storing of information. However, since the four-fold increase in integration results in only a 40% increase in the effective chip area, the area of the memory cell effectively decreases to one third its original size. This dictates that a conventional capacitor structure cannot realize a sufficiently large cell capacitance in the limited area. Therefore, in order to achieve larger capacitances in a smaller area, methods have been proposed which usually include decreasing the thickness of the dielectric film, using a material with a large dielectric constant as the dielectric material, and increasing the effective area of the capacitor's storage electrode.
If the thickness of the dielectric film is brought below 100 .ANG., the reliability of the semiconductor memory device is diminished due to the leakage current caused by Fowler-Nordheim tunnelling. Accordingly, reducing the dielectric film's thickness is not suitable for large-capacitance memory device.
Also, a high-dielectric material may be used for the dielectric film of the capacitor. Ta.sub.2 O.sub.5, which has a good step coverage with respect to three-dimensional memory cell structures having large aspect ratios, is being widely studied. However, at present, applying a thin film of Ta.sub.2 O.sub.5 in products results in high leakage current and a low breakdown voltage. To overcome this, various efforts to develop other materials with high dielectric constants are being pursued but, as yet, no practical methods for applying them in semiconductor memory devices have been reached.
Thus, in order to achieve large capacitances for the above-mentioned smaller cell area, the method which has been studied most actively is the increase of the effective storage area of the electrode. Growing from the conventional planar capacitor cell, three-dimensional structures such as a stacked capacitor cell and a trench capacitor cell have been introduced and are now being applied to 4 Mb DRAMs. However, this method exhibits limitation beyond 16 Mb DRAMs. In the stacked capacitor cell, due to the stacked capacitor structure, the step difference problem is serious, while in the trench capacitor cell, leakage current between trenches is created due to the scaling down. Accordingly, this method is difficult to apply in 64 Mb DRAMs.
Therefore, to solve the problem of large-capacitance DRAM cells, new capacitor structures such as the stacked trench capacitor, fin-structured capacitor, box-structured capacitor and spread-stacked capacitor are being considered. However, attempts to increase capacitance by improving storage electrode structure are limited in the development of next-generation devices having higher integration due to design rule limitations and complicated processing. This requires the development of a new capacitor structure which overcomes such problems.
To meet such a requirement, a method has recently been suggested in which increasing a capacitor's capacitance does not depend upon the structural improvement of a storage electrode, but upon an uneven topography of the surface of the storage electrode so that the effective capacitance area of the storage electrode is thus increased.
For instance, a paper entitled "Capacitance-Enhanced Stacker-Capacitor with Engraved Storage Electrode for Deep Submicron DRAMs" (by T. Mine et al., Extended Abstract of the 21st conference on Solid State Devices and Materials. Tokyo, 1989, pp. 137-140) discloses a method in which a mixture of SOG (spin-on-glass) and resist is formed on a polycrystalline silicon (hereinafter referred to as "polysilicon") layer. In this method, the SOG is selectively removed using a buffered HF solution to leave resist particles on the polysilicon layer, and the polysilicon layer is then etched using the resist particles to make the surface of the polysilicon layer topographically uneven.
U.S. Pat. No. 5,068,199 by Sandu discloses a method in which the storage electrode of a capacitor is formed using a porous polysilicon conductive layer to make the surface of the storage electrode uneven using an anodization.
U.S. Pat. No. 5,112,773 by Tuttle discloses a method in which a material for creating a heterogenous nucleation is implanted, or the deposition temperature or pressure is increased, to create uniform nucleation in the silicon source itself so that the polysilicon is deposited using vapor nucleation, to thus make the polysilicon layer uneven.
Further, another method has been suggested for forming an uneven polysilicon layer by adjusting the deposition condition of the polysilicon layer. Papers entitled "A New Stacked Capacitor Structure Using Hemispherical-Grain (HSG) Polysilicon Electrodes" (by H. Watanabe et al., SSDM, 1990, pp. 873-876) and "Fabrication of Storage Capacitance-Enhanced Capacitor with a Rough Electrode" (by Yoshio Hayashide et al., SSDM, 1990, pp. 869-872) disclose techniques in which a polysilicon layer having an uneven surface is formed at a predetermined temperature and under a predetermined pressure, and a storage electrode is formed using the polysilicon layer so that the surface of the storage electrode is increased due to the uneven surface of the polysilicon layer, thereby increasing the cell capacitance. Specifically, when the polysilicon layer to be used as the storage electrode is deposited at 550.degree. C. (which is the phase transition temperature in which amorphous silicon changes to a polysilicon) using low pressure chemical vapor deposition (LPCVD), the surface of the obtained polysilicon layer has hemispherical grains (hereinafter referred to as an "HSG polysilicon layer"), which approximately doubles the surface area. Hayashide et al. teach that when the storage electrode is formed by depositing the polysilicon at 575.degree. C., the capacitance increases to about one and a half times that of conventional polysilicon electrodes. Furthermore, Japanese Patent Laid-Open Publication No. Hei 1-42161 discloses a method in which the polysilicon layer formed according to the above method is used to form a storage electrode.
However, when employing the methods for making the storage electrode uneven using HSG polysilicon layer or other methods, though the surface of the polysilicon layer is approximately doubled, the effective area of a storage electrode for obtaining the cell capacitance required in very large scale integration (VLSI) semiconductor memory devices (above 256 Mb) still cannot be obtained.
Therefore, in order to solve such problems, Chin et al. (including one of the present inventors) invented a manufacturing method for a semiconductor memory device comprising a newly structured storage electrode required for VLSI semiconductor memory devices, and have filed the invention as U.S. patent application Ser. No. 07/937,749.
FIGS. 1, 2 and 3 are schematic views for explaining the method disclosed in the above patent application and show a storage electrode, dielectric layer and plate electrode only, which are the components of a capacitor of a semiconductor memory device. When this capacitor is applied in an actual memory cell, it is obvious to one skilled in the art that the storage electrode should be connected to the source region of a transistor which is a switching device. Therefore, the description and depiction of the preceding step in which the storage electrode and source region are connected, will be omitted.
FIG. 1 shows a step of forming a mask layer 11. Referring to FIG. 1, in order to form a storage electrode, an oxide is deposited on a conductive layer 10 having an uneven surface made of polysilicon hemispherical protrusions to form a mask layer 11 which is thicker than the depth d of valleys 15 between the hemispherical protrusions, such that the valleys are buried underneath the mask layer 11. Here, though not shown in the figure, a transistor as a switching device is formed under conductive layer 10 which is connected to the source region of the transistor.
FIG. 2 shows a step of forming an etching mask 11' by etching back mask layer 11. After forming mask layer 11, mask layer 11 is etched back until the upper surface of the hemispherical protrusions of the polysilicon is exposed so that the oxide which forms mask layer 11 is left in valleys 15 to thereby form etching mask 11'.
FIG. 3 illustrates a step of forming a capacitor by etching conductive layer 10 using etching mask 11'. More particularly, when conductive layer 10 is etched to a predetermined depth using etching mask 11' formed in valleys 15 of depth using etching mask 11' formed in valleys 15 of conductive layer 10, as shown in the figure, storage electrode 10' in the form of microtrenches and/or micropillars is formed. Dielectric layer 12 and plate electrode 13 are formed on storage electrode 10' to complete the capacitor.
FIGS. 4-9 sequentially illustrate an embodiment of a method for manufacturing the semiconductor memory device described in the above-noted U.S. patent application.
FIG. 4 shows a step of forming a transistor, planarization layer 20, first insulating layer 21 and second insulating layer 22. More particularly, a field oxide layer 42 for defining an active region and an isolation region is formed on semiconductor substrate 40 having a first conductivity. Source region 44 and drain region 46 are formed in the active region of semiconductor substrate 40 by a conventional process. Gate electrode 48 and word line 48' are formed on the active region and field oxide layer 42, respectively, to complete the transistor. Thereafter, planarization layer 20 is formed by depositing an insulating material, for instance, boro-phosphorus silicate glass (BPSG) or an oxide on the whole surface of the transistor structure and then planarizing it. First insulating layer 21, (for instance, a nitride layer having a thickness of about 500 .ANG.-1,000 .ANG.), and second insulating layer 22, (for instance, an oxide layer having a thickness of about 1,000 .ANG.-2,000 .ANG.), are formed sequentially on planarization layer 20. Here, reference number 49 indicates an insulating layer for insulating gate electrode 48 and word line 48'. The nitride layer of the insulating layer 21 will be used as an etching stop layer in the succeeding step.
A photoresist is coated on second insulating layer 22 to form a photoresist layer (not shown) which is then exposed using a mask. The exposed photoresist layer is developed to form a photoresist pattern. Using the photoresist pattern, the second insulating layer 22, first insulating layer 21, and first insulating interlayer 20 are etched to form first contact hole CH1 for connecting the storage electrode used for the first electrode of the capacitor to source region 44 of the transistor. Subsequently, the photoresist pattern for forming the first contact hole is removed and then polysilicon having hemispheric grains doped with an impurity is deposited to a thickness of 2,000 .ANG.-6,000 .ANG. on the whole surface of the resultant, to thereby form first conductive layer 24. Here, the surface of the conductive layer has a texture in which the grains are kept in close contact. However, it does not matter if the grains are somewhat separated from one another.
FIG. 6 shows a step of forming a first conductive layer pattern 24' and third insulating layer 26.
A photoresist is coated on first conductive layer 24 to form a photoresist layer. Using a photomask, the photoresist layer is exposed and the exposed portion thereof is developed to form a predetermined photoresist pattern (not shown). Using this photoresist pattern as an etching mask, first conductive layer 24 is etched to form first conductive layer pattern 24' as depicted. Subsequently, the photoresist pattern is removed and a high temperature oxide (HTO) is deposited to a thickness of, for instance, 300 .ANG.-1,000 .ANG., on the overall resultant structure to form third insulating layer 26.
FIG. 7 illustrates a step of etching the third insulating layer. After the step shown in FIG. 6, the overall resultant structure is etched back until the tops of grains of the polysilicon constituting first conductive layer pattern 24' are exposed to form an etching mask 26' made of the HTO in the valleys between grains of the polysilicon constituting first conductive layer pattern 24'. Here, spacers 26a made of the HTO are formed on the sidewalls of conductive layer pattern 24'.
FIG. 8 shows a step of forming a storage electrode SE. First conductive layer pattern 24' is etched to form storage electrode SE using etching mask 26' formed in the valleys between the hemispherical polysilicon grains constituting first conductive layer pattern 24' and spacers 26a formed on the sidewalls of first conductive layer pattern 24'. Particularly, first conductive layer 24' under the etching mask 26' is not etched, and microtrenches MT are formed in the portion where the etching mask is not formed so as to, as shown in the figure, form storage electrodes SE made of a pattern including microtrenches MT or micropillars MP. Here, the etching of the first conductive layer pattern 24' is performed with a mixed gas of HBr and Cl.sub.2 which has a high etching selectivity ratio with respect to the HTO used as the etching mask.
FIG. 9 shows a step of forming a capacitor C. After the step shown in FIG. 8, buffered oxide etchant (BOE) or diluted HF solution is used to remove etching mask 26' and spacers 26a made of the HTO, and a dielectric layer 30, (for instance, an ONO layer having an oxide/nitride/oxide structure or a NO layer having a nitride/oxide structure) is coated on the surface of the exposed storage electrode. Sequentially, polysilicon doped with an impurity is deposited on dielectric layer 30 and patterned to form a plate electrode PE. As a result, the capacitor comprised of storage electrode SE, dielectric layer 30 and plate electrode PE is completed. Subsequently, the drain region is exposed to form a bit line (not shown). Here, the bit line may be formed before the formation of the first conductive layer for forming the storage electrode.
In the storage electrode forming method disclosed in the above-described U.S. patent application, a timed etching (in which the etching step is performed for a predetermined time) is used for the step of forming an etching mask for forming the microtrenches. However, due to the variation of the thickness of the mask layer (reference numerals 11 and 26 in FIG. 1 and in FIG. 6, respectively) used as the etching mask and the variation of the etching rate according to etching equipment, it is difficult to form an etching mask (reference numeral 11' of FIG. 2 and reference numeral 26' of FIG. 7) to form microtrenches having a predetermined uniform thickness. Furthermore, cell capacitance is limited because the surface of the storage electrode is increased only by as much as the formation of microtrenches and/or micropillars.